Electrical Albelazi. – Mohammed Attir. Part I: key


Electrical and Electronics




Analysis of the PC/XT Motherboard

Done by:

Yasmin Albaili.

Muad Albelazi.

Mohammed Attir.












Part I: key components:

The board overall is composed as follows:

The top left, there is a
power connector for the whole motherboard. Next to that is the only i/o
included in the motherboard which is a 5-pin custom connector for the keyboard.

On the top center, there
are to 2 40-way sockets for the processing units, one is already occupied by
the intel 8088 processor, and the other is an optional slot for the IBM math
processor which was not included on the board.

On the left side of the
board there are the expansion slots for any external devices to be connected to
such as hard drive controllers, graphics cards or diskette adapters.

Hard Drive controllers were necessary at
that time since the hard drives did not have any logic on them for issuing
addresses or write/ read commands, instead there were some external cards to be
connected to issue these commands if one wishes to install an external mass
storage unit.

On the bottom right, the main
memory (RAM) is located as individual chips with parity checking on the whole
data entering the memory. 9 empty slots were included for the consumer to allow
future expansion of memory size. However, one should consider that this board
support memory size of 128K to 640K only, a higher value than that would
require an external card to be connected through the expansion slots with
slightly higher access time than the modules included.

Next to the processor on
the left side, there is a small dip switch, this is used to configure the
system before it starts. It provides the system programs with information about
the installed options, how much storage the system board has, what type of
display adapter is installed, indicates if the coprocessor is installed or not,
what operational modes are desired when power is switched on (color or
black-and-white, 80- or 40-character lines), and the number of diskette drives

Going into details of some of the visually identifiable

The empty 40-way slot
in the top middle of the board:

It is used for a special math microprocessor
developed by the manufacturer IBM to work with the 80xx main processor, which
was not included from the factory.


The v20 Processor:

This processor was reversely-engineered by a
company called NEC to be pin compatible with the 8088 socket, hence, it is used
as an upgrade for the 8088. It runs approximately 30% (application dependent)
faster than the 8088 since it has more transistors built in, faster loop
counters and faster shift registers and multipliers.


The 8255 IC:

It is a programmable peripheral interface
that was developed and designed by intel to work with their 80xx processors. It
provides 24 parallel input/output lines to show commands/mode registers on the
system board. It also supports various programmable modes of operation.

5515 technical reference).


The 8237 IC:

It is a high performance direct memory
access (DMA) chip which enables the data to be transferred between the i/o
devices and the main memory directly. Consequently, it reduces the stress on
the main processor by doing its job in controlling the memory address data
during its transfer between the i/o and the main memory. It has 4 channels, 3
of these are available to the I/O bus and support high speed data transfer, and
the last one is used to refresh the system’s DRAM since DRAM loses the charge
that is stored in it after a while and need a periodic recharge process.

(IBM 5515 technical reference)



The 27C512 chip:

It is a 64K EPROM chip (erasable
programmable read only memory) and it is used in this motherboard to store the
BIOS of the system (the BIOS is a set of tests that the computer performs as
soon as it is turned on to ensure that all the hardware is functioning well).
This ship can be programmed only once, so if one wishes to reprogram it, one
must replace it with a new one. There are some available slots for an

SHEET+ IBM 5515 technical reference).


8259 IC:

It is a programmable interrupt controller
PIC. It is used to control the CPU interrupt mechanism by accepting several interruptions
requests an ordering them to be received by the CPU. The interruptions are
usually divided in 2 levels, level 0 is higher priority which provides
periodic interruptions for the time of the day. Level 1 is attached to
the keyboard adapter circuit to receive an interruption for each input from the

( http://wiki.osdev.org/8259_PIC)(DATE  ( DATE: 29/12/2017)
(IBM 5515 technical reference)



8253 IC:

It is a chip that was designed by intel to
operate with the 80xx processors series. It is a programmable interval timer
which consists of an oscillator and 3 frequency dividers (counters) to perform
the counting functions for the CPU. It can handle clock speeds up to 10MHz.

(http://wiki.osdev.org/Programmable_Interval_Timer)  (DATE: 29/12/2017).



ISA expansion slots:

ISA stands for (industry standard
architecture) which is an expression associated with the IBM computers that
were based on the intel 80xx series of processors. The expansion slots that are
located on the left part of the board, which were 8-bits according to the ISA
back then, and were available for the user to connect I/O devices such as monitors
through graphics cards, hard drives controllers, or diskette adapters (floppy

(DATE 29/12/2017)


The UD61256
Memory Module:

It is a dynamic random-access memory ship
of size 256K bytes. This motherboard has already 27x memory modules installed,
the extra 9 empty slots are for future main memory expansion. (IBM 5515
technical reference + DATA SHEET).






Part 2: Memory analysis in IBM TX PC.

RAM Subsystem:

The IBM PC/XT motherboard has the RAM located in the lower
left part f the it. It is a DRAM type. It is composed of 27x 256K Read/Write
memory modules. The memory access time is usually outlined as 150 nanoseconds
and the cycle period is 275 nanoseconds (Mano, 2008). Furthermore, the memory
refreshes demand one memory cycles every 15 microseconds via the DMA IC (8237
that was mentioned in part 1) (Mano, 2008). The role of RAM in initializing
programs usually performs functions such as initialization of channel 1 of the
timer to the degree of 15 microseconds. Besides that, the RAM usually performs
the memory write operations to any memory location. It is also important to
note that memory should be refreshed eight times before it was used (Mano,


The CPU of IBM TX and communication of Key Ideas in
relation to Memory:

The 8080 processor is present in IBM PC TX. The processor is
composed of 8-bit external data bus and the 16 bits of 8086.The 16-bit
registers and the presence of one-megabyte address range usually remain
untouched. Both 8080 and 8086 are composed of a similar execution unit as well
as the bus interface unit (Keates, Varker and Spowart, 2011). With respect to
memory, the processors that are used to execute instructions are based on 8080
and 8086.This means that the two types of processors seem to have different
sizes of instructions sets that makes them have different execution levels (Mano,


ADO-7 Connection With respect to memory:

Concerning the IBM TX PC, the connection of ADO-7 is a
connection used to show how devices that drive the data bus. In this section,
only the data routes that need to be evaluated vs. the loading analysis whereby
paths idle usually loads on the bus. The role of data bus is to make sure
memory is well served with all instructions that need to be stored.AD0-7 is in
short termed as the bus that directs various instructions to the memory to
ensure instant feedback is provided (Mano, 2008).


A8-A19 with respect to memory:

Concerning this type of connection in the IBM TX PC, it can
be outlined that the sole role of such connection is to processors to access
memory (Keates, Varker and Spowart, 2011). In our case, processors might be
8080 and 8086 whereby they share A8-A19 for purposes of obtaining the memory.


NMI with respect to memory:

The role of this section in the IBM TX is to provide the
interrupts. This is done to avoid waiting for one instruction set from the main
memory and the CPU is tasked to do another pending work before entire
instructions are executed. This makes the memory to be well managed since when
task is being used, the memory can be used to perform other storage tasks. The
role of MASK On NMI is to write the I/O address hex 070 with data bit that is
equivalent to logical 1.On the other hand, the MASK OFF is used to write
address hex with a data bit  7
equivalents  to logical 0 (Mano, 2008).

When a check takes place, MI reads the condition of the bits
to come up with the determination of the source of NMI. To define the position
of the failing connector and write to any given memory position within a
particular connector (Mano, 2008).


RD with respect to memory:

In the IBM TX PC motherboard, the presence of RD connection
is of great importance. This is because RD performs the role of showing the
device that is being used by the CPU. For example, when the single line
indicates zero, this means that CPU is being used (Keates, Varker and Spowart,
2011). As a result, the management of all instructions that need to be stored
in the memory is sequential due to the fact that RD connection flags the
processes that are currently running in the CPU (Mano, 2008).


WR with respect to memory:

In IBM processor, the WR is a single line that usually
denotes when active by use of logic zero to outline that the device is being
written by the CPU. Furthermore, the use of RD and WR signals usually control
the reading or writing of the Random-Access Memory.



ALE as a component of the CPU acts as a control signal. It
is usually associated with 8086 processor. The role played by ALE is to
multiplex the data bus and the low order addresses. ALE functions in a manner
that arranges the sequent of instructions from and into the memory by providing
the low and high order addresses (Mano, 2008). The ability to disable and
enable address bus means that ALE connector has direct management of the





Part 3: Glue Logic:


It is an octal bus transceiver with 3
states output which are designed for asynchronous two ways communication
between data buses and it consists of a control function implementation that
minimizes external timing requirements.it is often used as an amplifier. In
other words, when adding a large quantity of circuitry on the board, the CPU’s
data buses would be loaded down therefore a buffer is added to prevent any
overloading applied on the CPU and also to buffer the signals out and in the


Logic circuit                                                                    *        TOP VIEW



2-      74ls373:

It is a
transparent lath consists of 8 latches with 3 states output for bus organized
system applications and comprises 8 D flip flops through which the input is
given to the each pin of the IC. Whenever data is sent out by the CPU via data
bus the data must be latched and the main propose of the D flip flops is that
any input at the present state will be given as an output in the next clock
cycle. That is what the 74LS373 is used for (Latching data).







3-      74LS74 ( U86 AND U73

The 74LS74A is a dual D-type positive edged
triggered flip flop with the availability of the preset in clear pins, the data
at inputs are transferred to the output on the positive going edege of the
clock pulse (this happens for both 74LSxx A and AN). The 74LS74A is known as
the low power schottky while the 74LS74AN is a dual D-type positive edged
triggered flip flop but without the availability of the preset. The ICs were
used to store data, to control the display and also to introduce a delay when
it is needed.



4-      74LS280 :

It a 9 bit even/odd parity generator checker is a
design which permits the LS280 to be substituted for the LS180. It is used to
check for any parity error when the memory is in read state which gives
reliability for the data stored in memory.





Keates, S., Varker, P. and
Spowart, F. (2011).

Human-machine design
considerations in advanced machine-learning systems.

IBM Journal of Research and
Development, 55(5), pp.4:1-4:10.

Mano, M. (2008).

Computer system

New Delhi: Prentice-Hall of